Memory devices, such as non-volatile (NV) memory devices and/or storage devices, may be required to operate in different power modes. The power modes may be defined by one or more standards. A host computing system may instruct the memory device to transition between different power states in accordance with a power policy and/or the like. The host computing system may request that the memory device transition to a low-power state in response in order to, inter alia, reduce the rate at which power is being consumed by the host computing system. The host computing system may request the memory device to transition to a low-power state as part of an upper-level power management operation, such as a “sleep,” “suspend,” “hibernate,” “shutdown” or other operation. The host computing system may request the memory device to transition to a higher-power state in response to another upper-level power management operation, such as a “wakeup,” “resume,” “restart,” or the like.
Power states may be defined by the host and/or one or more standards. For example, the non-volatile memory express (NVMe EXPRESS) standard defines various device power states, each of which may correspond to a respective use case. The power states may include PS0 through PS4, where PS0 is an active power state (a power state in which the memory device is operational). During operation in the PS0 power state, the memory device may be allowed to consume more power than when in other, lower-power states. Other power states PS1-PS4 may have gradually decreasing power specifications and/or may correspond to non-operational state(s) of the memory device. As used herein, a “non-operational” state refers to a power state in which one or more services of the memory device are non-operational and/or the memory device is not configured to process commands directed thereto. As used herein, an “operational state” refers to a state in which services of the memory device are operational and/or the memory device is configured to receive and/or process commands. PS0 -PS2 may comprise operational states, and PS3-PS4 may comprise non-operational states.
The power states may have respective time and/or power requirements, which may define an acceptable latency for transitioning to/from a respective power state, the amount of power available to the memory device during the transitions, the amount of power available to the memory device while in the respective power state, and so on. For example, the specification(s) for the PS3 power state may require the memory device to make rapid transitions to/from the PS3 power state, but may allow the memory device to impose specified transactional power costs when making such transitions. In other power states, the memory device may be restricted to lower-power consumption levels, but may be allocated more time for power state transitions. For example, in the PS4 power state, the memory device may be expected to have minimal power consumption (on the order of 2 to 5 milliwatts), but may be permitted to take more time for transitions into and/or out of the PS4 power state. The transitional latency and/or power consumption estimates are be defined in a specification implemented by the memory device, the host computing system, an interconnect to which the memory device is coupled, and/or the like. As disclosed above, the power state specification(s) may be used as part an upper-level power strategy in order to optimize power consumption of the host computing system (e.g., maximize the battery life of portable computing systems).
A memory device may comprise integrated onboard DRAM, such as DDR2/3/4 or LPDDR2/3. Using onboard DRAM may enable a memory device to rapidly transition to/from the PS3 power state by, inter alia, transferring the operating state of the memory device to the DRAM and/or retaining the contents of the DRAM while the memory device is transitioned to the PS3 state. The memory device may quickly resume from the PS3 state by, inter alia, reading the operating state information from the on-board DRAM. Similarly, in transitions to and from the PS4 state, DRAM may be maintained in self-refresh mode (full array or partial array as in LPDDR devices) so that device context information can be retrieved from the DRAM during startup. However, on-board DRAM may be expensive and it may not be practical to maintain the DRAM while in certain low-power states. As such, transitioning to lower-power states may require the operating state of the memory device to be written to NV memory, which may increase the latency required for transitioning to such lower-power states. Moreover, resuming from the lower-power state may require the memory device to read the operating state from the NV memory, which may increase the latency of resume operations (on the order of about 300 milliseconds, or more, for transitioning to a low-power state, such as PS4, and about 100 milliseconds, or more, from resuming from the low-power state). Therefore, what are needed are systems, methods, and apparatus for efficiently transitioning between power states.